Position: Senior DFT Engineer

Responsibilities:

1. Responsible for implementing design-for-testability (DFT) techniques and participating in the design and development of complex IPs and SoCs.
2. Design and implement DFT features for SoCs, including but not limited to SCAN, Boundary SCAN, MBIST, etc.
3. Responsible for generating high-coverage and cost-effective test patterns to ensure the quality of production testing.
4. Collaborate with the team to participate in defining DFT features and architectures for full-chip designs.
5. Address technical challenges during the DFT process to ensure timely project completion.

Requirements:

1. Proficient in ASIC frontend design processes, including logic design, synthesis, DFT, and static timing analysis.
2. Solid theoretical and practical experience in DFT, with familiarity in various DFT techniques.
3. Familiar with mainstream DFT tools such as Cadence, Synopsys, or Mentor.
4. Strong programming skills, capable of using scripting languages like Tcl/Tk/Python for design and testing tasks.
5. Good communication skills and a collaborative mindset, able to work under pressure and solve technical problems.
6. Relevant industry experience is preferred, such as experience in automotive or AI chip 3D design domains.